Job Title Team lead: Layout design of High Speed SerDes test chips
Job Information

Looking for high caliber, collaborative, energetic, committed people to help establish us as a world leading technology enabler.
To perform the layout design of critical High speed Circuit designs at block /& chip level for our High speed connectivity chips.Monitor, track and advice on module level layout designs development by engineers.
Floor planning, ESD, bump planning, top level integration & chip finishing checks are to be taken care.

Education Qualification

Advanced diploma in VLSI/ BE/ME with 6+ years of relevant experience.

Hands on tool expertise

Tools: cadence virtuoso, verification tools like PVS, calibre, QRC, PEX and proficiency in skill coding.

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