Design/verify the RTL code for the high speed SerDes related digital blocks. Verilog RTL/behavioral coding exprience is essential.
Should be conversant with the interface protocols like USB, Mphy, PCIE, JEDEC etc.,
VerilogA, Verillog AMS coding skills will be preferred.
Synthesis/timing closure exposure,LEC, SDC file creation experience is preferred.

Education Qualification

BE/ME with 5+ years of relevant experience

Hands on tool expertise

Tools: cadence RC,nclaunch, simvision, mdelsim