Responsible for the design and architecture development of the blocks related to SerDes
Responsible for top level integration of the test chips
Monitor, track and advice on modue level development by engineers.
Interface with the customers/foundry for collection of inputs and quality of the deliverables

Education Qualification

M.Tech in VLSI/ECE with Analog circuits specialization
10 years of relevant experience

Hands on tool expertise

Tools: cadence schematic, layout, simulation and verification tools and proficiency in MDL scripts and skill coding.